This invention relates to the manufacture of MIS capacitors for semiconductor IC devices, and more particularly to a method of manufacturing MIS capacitors adapted for use in dynamic MOS memory IC devices.
In conventional dynamic random access memories (DRAM) of one transistor/one capacitor type, silicon dioxide (SiO.sub.2) is mostly used as the dielectric material of the memory cell capacitor. With recent increasing demand for higher packing density of DRAM IC's, the component elements have been becoming smaller in size. A MIS (Metal Insulator Semiconductor) capacitor for the memory cell should have a capacitance value above a certain level despite its reduced size, so as to prevent soft error due to alpha rays and to insure stable operation of the memory circuit.
Two measures are known as effective to increase the capacitance of such a small-area MIS capacitor. One is to reduce the thickness of the dielectric layer, and the other is to use a dielectric material with a high dielectric constant as the capacitor dielectric material. However, reduction of the dielectric layer thickness can result in increased pin holes in the layer, leading to degraded dielectric strength and consequently low yield of the memory IC. On the other hand, silicon nitride (Si.sub.3 N.sub.4) or tantalum oxide (Ta.sub.2 O.sub.3) is conventionally used as the high dielectric-constant dielectric material. However, the use of these materials in the form of a single dielectric layer can cause electrical unstableness of the memory IC device, increased leakage current, and reduced dielectric strength due to increased pin holes, etc.